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Produktbild: Timing Analysis and Optimization of Sequential Circuits
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Timing Analysis and Optimization of Sequential Circuits

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.10.1998

Abbildungen

XV, 190 p.

Verlag

Springer Us

Seitenzahl

190

Maße (L/B/H)

24,1/16/1,7 cm

Gewicht

489 g

Auflage

1999

Sprache

Englisch

ISBN

978-0-7923-8321-5

Beschreibung

Rezension

'
To sum it up it can be said that the authors have done a great job. The book is well written and can serve as a textbook for graduate students, researchers, and professionals in the area of CAD for VLSI and VLSI circuit design.
'




Zentral Blatt Mathematik, 987 (2002)

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.10.1998

Abbildungen

XV, 190 p.

Verlag

Springer Us

Seitenzahl

190

Maße (L/B/H)

24,1/16/1,7 cm

Gewicht

489 g

Auflage

1999

Sprache

Englisch

ISBN

978-0-7923-8321-5

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: ProductSafety@springernature.com

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  • Produktbild: Timing Analysis and Optimization of Sequential Circuits
  • 1. Introduction.- 1.1 Performance Optimization of VLSI Circuits.- 1.2 Outline of the Book.- 2. Timing Analysis of Sequential Circuits.- 2.1 Introduction.- 2.2 Combinational Delay Modeling.- 2.3 Clocking Disciplines: Edge-Triggered Circuits.- 2.4 Resolving Short Path Violations.- 2.5 Clocking Disciplines: Level-clocked Circuits.- 2.6 Clock Schedule Optimization for Level-Clocked Circuits.- 2.7 Timing Analysis of Domino Logic.- 2.8 Concluding Remarks.- 3. Clock Skew Optimization.- 3.1 The Notion of Deliberate Clock Skew.- 3.2 Is Clock Skew Optimization Safe?.- 3.3 Clock Tree Construction.- 3.4 Clock Skew Optimization.- 3.5 Clock Skew Optimization with Transistor Sizing.- 3.6 Wave Pipelining Issues.- 3.7 Deliberate Skews for Peak Current Reduction.- 3.8 Conclusion.- 4. The Basics of Retiming.- 4.1 Introduction to Retiming.- 4.2 A Broad Overview of Research on Retiming.- 4.3 Modeling and Assumptions for Retiming.- 4.4 Minperiod Optimization of Edge-triggered Circuits.- 4.5 Level-clocked Circuits.- 4.6 Concluding Remarks.- 5. Minarea Retiming.- 5.1 The Leiserson-Saxe Approach.- 5.2 The Minaret Algorithm.- 5.3 Minarea Retiming of Level-Clocked Circuits.- 6. Retiming Control Logic.- 6.1 Minperiod Initial State Retiming via the State Transition Graph.- 6.2 Minperiod Initial State Retiming via Reverse Retiming.- 6.3 Minarea Initial State Retiming.- 6.4 Maintaining Initial States With Explicit Reset Circuitry.- 7. Miscellaneous Issues in Retiming.- 7.1 Retiming and Testing.- 7.2 Verification Issues.- 7.3 Retiming for Low Power.- 7.4 Retiming with Logic Synthesis.- 7.5 Retiming for FPGA’s.- 7.6 Practical Issues.- 7.7 Conclusion.- 8. Conclusion.- References.