Vor Ort
Merkzettel Warenkorb
  • Produktbild: VLSI-SoC: From Systems to Silicon
  • Produktbild: VLSI-SoC: From Systems to Silicon
Band 240

VLSI-SoC: From Systems to Silicon IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia

Aus der Reihe IFIP Advances in Information and Communication Technology

92,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

22.08.2007

Herausgeber

Ricardo Reis + weitere

Verlag

Springer Us

Seitenzahl

344

Maße (L/B/H)

24,4/16,5/2,7 cm

Gewicht

646 g

Auflage

2007 edition

Sprache

Englisch

ISBN

978-0-387-73660-0

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

22.08.2007

Herausgeber

Verlag

Springer Us

Seitenzahl

344

Maße (L/B/H)

24,4/16,5/2,7 cm

Gewicht

646 g

Auflage

2007 edition

Sprache

Englisch

ISBN

978-0-387-73660-0

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: gpsr@libri.de

Noch keine Bewertungen vorhanden

Verfassen Sie die erste Bewertung zu diesem Artikel

Helfen Sie anderen Kundinnen und Kunden durch Ihre Meinung.

Kundinnen und Kunden meinen

Bewertungen (0)
  • Produktbild: VLSI-SoC: From Systems to Silicon
  • Produktbild: VLSI-SoC: From Systems to Silicon
  • Molecular Electronics – Devices and Circuits Technology.- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.- Defragmentation Algorithms for Partially Reconfigurable Hardware.- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.- Issues in Model Reduction of Power Grids.- A Traffic Injection Methodology with Support for System-Level Synchronization.- Pareto Points in SRAM Design Using the Sleepy Stack Approach.- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.- A Novel MicroPhotonic Structure for Optical Header Recognition.- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.- Exact BDD Minimization for Path-Related Objective Functions.- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.