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Produktbild: High Performance Embedded Architectures and Compilers
Band 5952

High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings

Aus der Reihe Lecture Notes in Computer Science

48,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

20.01.2010

Abbildungen

76 schwarz-weiße Abbildungen, Bibliographie

Herausgeber

Yale N. Patt + weitere

Verlag

Springer Berlin

Seitenzahl

370

Maße (L/B/H)

24,2/15,6/2,5 cm

Gewicht

584 g

Auflage

2010. Edition

Sprache

Englisch

ISBN

978-3-642-11514-1

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

20.01.2010

Abbildungen

76 schwarz-weiße Abbildungen, Bibliographie

Herausgeber

Verlag

Springer Berlin

Seitenzahl

370

Maße (L/B/H)

24,2/15,6/2,5 cm

Gewicht

584 g

Auflage

2010. Edition

Sprache

Englisch

ISBN

978-3-642-11514-1

Herstelleradresse

Springer-Verlag GmbH
Heidelberger Platz 3
14197 Berlin
Deutschland
Email: sdc-bookservice@springer.com
Url: www.springer.com
Telephone: +49 6221 3454301
Fax: +49 30 8214091

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  • Produktbild: High Performance Embedded Architectures and Compilers
  • Invited Program.- Embedded Systems as Datacenters.- Larrabee: A Many-Core Intel Architecture for Visual Computing.- Architectural Support for Concurrency.- Remote Store Programming.- Low-Overhead, High-Speed Multi-core Barrier Synchronization.- Improving Performance by Reducing Aborts in Hardware Transactional Memory.- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.- Compilation and Runtime Systems.- Split Register Allocation: Linear Complexity Without the Performance Penalty.- Trace-Based Data Layout Optimizations for Multi-core Processors.- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors.- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures.- Reconfigurable and Customized Architectures.- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions.- Accelerating XML Query Matching through Custom Stack Generation on FPGAs.- An Application-Aware Load Balancing Strategy for Network Processors.- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.- Multicore Efficiency, Reliability, and Power.- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors.- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors.- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.- Performance and Power Aware CMP Thread Allocation Modeling.- Memory Organization and Optimization.- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching.- Scalable Shared-Cache Management by Containing Thrashing Workloads.- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs.- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.- Programming and Analysis of Accelerators.- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor.- Analysis of Task Offloading for Accelerators.- Offload – Automating Code Migration to Heterogeneous Multicore Systems.- Computer Generation of Efficient Software Viterbi Decoders.