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  • Produktbild: Static and Dynamic Performance Limitations for High Speed D/A Converters
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Static and Dynamic Performance Limitations for High Speed D/A Converters

Aus der Reihe The Springer International Series in Engineering and Computer Science

146,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

09.12.2010

Verlag

Springer Us

Seitenzahl

218

Maße (L/B/H)

23,5/15,5/1,4 cm

Gewicht

373 g

Auflage

Softcover reprint of the original 1st ed. 2004

Sprache

Englisch

ISBN

978-1-4419-5434-3

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

09.12.2010

Verlag

Springer Us

Seitenzahl

218

Maße (L/B/H)

23,5/15,5/1,4 cm

Gewicht

373 g

Auflage

Softcover reprint of the original 1st ed. 2004

Sprache

Englisch

ISBN

978-1-4419-5434-3

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

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  • Produktbild: Static and Dynamic Performance Limitations for High Speed D/A Converters
  • Produktbild: Static and Dynamic Performance Limitations for High Speed D/A Converters
  • Abstract. List of Symbols and Abbreviations.
    1: Introduction. 1.1. Introduction. 1.2. Outline of the Research Work.
    2: The D/A Converter: Functionality and Specifications. 2.1. Introduction. 2.2. The Basic D/A Converter Function. 2.3. The Characteristics of an Ideal D/A Converter. 2.4. The Performance Specifications of a D/A Converter. 2.5. The D/A Converter Specifications as a Function of the Application. 2.6. Conclusions.
    3: CMOS D/A Converter Architectures. 3.1. Introduction. 3.2. The Resistor D/A Converter. 3.3. The Capacitor D/A Converter. 3.4. The Current-Steering D/A Converter. 3.5. Conclusions.
    4: Static Behaviour of Current Steering D/A Converters. 4.1. Introduction. 4.2. Modelling of the Random Errors. 4.3. Modelling of the Systematic Errors. 4.4. Conclusion.
    5: Dynamic Behaviour of Current Steering D/A Converters. 5.1. Introduction. 5.2. Major Contibutors. 5.3. SFDR-Bandwidth Limitations. 5.4. SFDR-Bandwidth Optimised Implementations. 5.5. Conclusion.
    6: A Design Methodology for High Performance CMOS Current Steering D/A Converters. 6.1. Introduction. 6.2. Determining the Level of Segmentation in a Current Steering D/A Converter. 6.3. Architectural Choice of the Thermometer Decoder. 6.4. Design of the Synchronised Switch Driver. 6.5. Dimensioning the Unit Current Cell. 6.6. Conclusion.
    7: Realisations. 7.1. Introduction. 7.2. High Accuracy D/A Converters. 7.3. High Speed D/A Converters. 7.4. High Speed, High Accuracy D/A Converters. 7.5. Low Power, High Speed D/A Converters. 7.6. Overview of Realised DACs. 7.7. Comparison with Literature. 7.8. Conclusion.
    8: Transistor Mismatch: Evolution and Relevance. 8.1. Introduction. 8.2. Model of Lakshmikumar. 8.3. Model of Pelgrom. 8.4. Other Models. 8.5. Mismatch Parameters for the 0.5 and the 0.4 &mgr;m CMOS Technology. 8.6. Transistor Mismatch Dependency on its Geometry. 8.7. Influence of the Surroundings of the Transistors on the Mismatch Behaviour. 8.8. The CMOS Current Steering D/A Converter as a Test Structure for Transistor Mismatch Parameter Extraction. 8.9. Conclusion.
    Appendix 1: Appendix 2: Bibliography.