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Produktbild: Fundamentals of VHDL for FPGA Programming Using Vivado

Fundamentals of VHDL for FPGA Programming Using Vivado

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

01.12.2025

Verlag

John Wiley & Sons

Seitenzahl

416

Maße (L/B/H)

25,9/18,3/2,8 cm

Gewicht

882 g

Sprache

Englisch

ISBN

978-1-394-34309-6

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

01.12.2025

Verlag

John Wiley & Sons

Seitenzahl

416

Maße (L/B/H)

25,9/18,3/2,8 cm

Gewicht

882 g

Sprache

Englisch

ISBN

978-1-394-34309-6

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: gpsr@libri.de

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  • Produktbild: Fundamentals of VHDL for FPGA Programming Using Vivado

  • About the Author xi

    Preface xii

    Acknowledgments xiii

    About the Companion Website xiv

    1 Overview 1

    1.1 Introduction 1

    1.2 Introduction to VHDL 2

    2 Creating a Project in Vivado 5

    2.1 Introduction 5

    2.2 Creating a Project 5

    3 The VHDL Design Structure 13

    3.1 Introduction 13

    3.2 The VHDL Keywords 13

    3.3 The VHDL Libraries 19

    3.4 The VHDL Entities and Architecture 25

    3.5 The VHDL Generics 27

    4 The VHDL Statements and Data Types 31

    4.1 Introduction 31

    4.2 The VHDL Data Types 32

    4.3 The VHDL Integers 35

    4.4 The When-Else Statement 36

    4.5 Concurrent Versus Sequential Statements 37

    5 The Simulations in Vivado 41

    5.1 Introduction 41

    5.2 The Shift Register Design 42

    5.3 Shift Register Test Bench Design 44

    5.4 Vivado Simulator Tool Introduction 46

    5.5 Running a Simulation in Vivado 47

    5.6 Navigating Vivado Simulations 52

    6 The Buttons and LEDs Project 61

    6.1 Introduction 61

    6.2 Buttons and LEDs Complete Design Walk-through 61

    6.3 The Button_LED Arty A7 IO Placement 63

    6.4 Generate a Xilinx Programming File 66

    6.5 Simulation of Button_LED Project 71

    7 The Blinky LEDs Project 75

    7.1 Introduction 75

    7.2 Constants and Signals 75

    7.3 The VHDL Processes 78

    7.4 The VHDL If Statements 81

    7.5 The If Statement Priority Example 85

    7.6 The Blinky LEDs Project IO Placement 90

    8 The LED Brightness Project 93

    8.1 Introduction 93

    8.2 The PWM VHDL Design 94

    8.3 The VHDL Generate Statement 101

    8.4 The Counter Design 103

    8.5 The VHDL Component Instantiations 110

    8.6 The LED Brightness Arty A7 IO Placement 120

    9 The UART Demonstration Project 125

    9.1 Introduction 125

    9.2 The MicroBlaze Softcore Processor 129

    9.3 The Xilinx Software Development Kit 133

    9.4 The UART Demonstration Arty A7 IO Placement 146

    10 The UART IO and Register Access 149

    10.1 Introduction 149

    10.2 The UART IO Complete Design 153

    10.3 The UART IO Arty A7 IO Placement 160

    11 The ADC Processing Project 163

    11.1 Introduction 163

    11.2 Using the Xilinx XADC and MicroBlaze MCS 166

    11.3 The MicroBlaze MCS ADC Configuration 171

    11.4 Interfacing with the XADC Core 172

    11.5 The ADC Processing Arty A7 IO Placement 181

    12 The SPI Interface Project 183

    12.1 Introduction 183

    12.2 Overview of the SPI Interface 186

    12.3 The SPI Interface Design Strategy 189

    12.4 External SPI Flash Chip Memory Organization 191

    12.5 The SPI Configuration and File Generation 193

    13 Some Miscellaneous Projects with Vivado 197

    13.1 Introduction 197

    13.2 The I2C Interface Project 197

    13.3 The VHDL CORDIC Sine-Cosine Generator 199

    13.4 The Trailing Edge PWM in VHDL 204

    13.5 The LUT-based Sine Wave in VHDL 219

    13.6 The Symmetrical PWM in VHDL 229

    14 Generating VHDL Code for Vivado Using Simulink HDL Coder 247

    14.1 Introduction 247

    14.2 The Half Adder Circuit Design 247

    14.3 Sequential Circuit and State Flow Chart Modeling 253

    14.4 The Basic PWM Design 262

    15 Application of Flowcharts in Simulink for VHDL Code Generation 271

    15.1 Flowchart of Multiplier 271

    15.2 Flowchart of GCD Calculator 283

    15.3 Flowchart of Booth's Multiplication 291

    15.4 Flowchart of an Industrial Control System 299

    16 Machine Learning Regression Model on FPGA 311

    16.1 Introduction 311

    16.2 The Kaggle Dataset 311

    16.3 Machine Learning Regression Model for Admission Dataset 311

    16.4 The Regression Model in Simulink 316

    16.5 Using Generated VHDL Code in Vivado 320

    17 Machine Learning Binary Classification Model on FPGA 327

    17.1 Introduction 327

    17.2 The Kaggle Dataset 327

    17.3 The Binary Classification (Logistic Regression) 327

    17.4 Machine Learning Logistic Regression Model for Dataset 329

    17.5 The Logistic Regression Model in Simulink 337

    17.6 Using Generated VHDL Code in Vivado 348

    18 Deploying a Deep Neural Network on FPGA 355

    18.1 Introduction 355

    18.2 The Kaggle Dataset 355

    18.3 Introduction to Neural Networks 355

    18.4 Piecewise Linear Approximation of Activation Functions 357

    18.5 Training the Neural Network Model 368

    18.6 Using Generated VHDL Code in Vivado 389

    Index 395